1. The Field of the Invention
The present invention relates to semiconductor device fabrication technology, and more specifically, to methods for protecting the sidewall of a metal interconnect during a subsequent plug fill of an unlanded via.
2. Background and Related Art
Computing technology has revolutionized the way people work and play and has contributed enormously to the advancement of humankind. Much of computing technology has been enabled by the discovery and advancement of semiconductor processing technology.
Semiconductor processing technology allows for the formation of highly integrated circuits with multiple metal layers. By constructing integrated circuits with multiple metal layers, a given circuit with given feature dimension sizes may be fabricated using much less space than it would if it was permitted just a single metal layer. Furthermore, multiple metal layers enables for much more efficient design and operation of the circuit.
In order for the metal interconnect components in different layers to have sufficient isolation and selective connection with each other, a dielectric layer such as silicon dioxide is formed between the metal layers during the fabrication process. A via is formed by etching the dielectric layer so that a portion of the lower metal interconnect component is exposed. The via is then filled with conductive material such as tungsten. The material structure that fills the via is often termed a “plug”. The upper metal interconnect component may then be formed to contact the via plug so that an electrical connection is made between the upper and lower metal interconnect components.
The vias are typically designed so that they are directly over the lower metal interconnect component with no overlap. Unfortunately, however, feature dimension sizes are so small that even state of the art alignment technology often results in some misalignment. For example, FIG. 8A illustrates a top view of a plug 802 and a lower metal interconnect component 801. Note how the plug 802 (identified by the box filled with the large X) overlaps the edge of the lower metal interconnect component 801. This type of overlapping misaligned via is often termed an “unlanded via”. The result of this misalignment may be apparent from FIG. 8B, which is a cross-sectional view of the plug 802 and lower metal interconnect component 801. FIG. 8B also shows the dielectric material 804 upon which the metal interconnect component 801 is constructed, as well as the dielectric material 803 which supports upper metal interconnect layers (not shown). Before the plug 802 is formed with an appropriate conductive material such as tungsten, the right sidewall of the lower metal interconnect component 801 (which may be, for example, Aluminum) is exposed.
In order to deposit the tungsten material, the device is exposed to a Tungsten Hexafluoride (WF6) gas under certain conventionally-known environmental conditions. The Tungsten forms within the via, while the Fluorine (F) atoms continue in gaseous form. Some of those Fluorine atoms may react with the Aluminum (Al) to generate Aluminum Tetrafluoride (AlF4), which will conduct for a short time, and then form an electrical discontinuity, thereby frustrating the operation of the circuit.
In order to protect against the harmful reaction between the Aluminum metal interconnect component and the Fluorine gas, a Titanium Nitride layer is often deposited on top of the Aluminum metal interconnect component prior to forming the dielectric layer and the via over the metal interconnect component. This serves the dual purpose of an antireflective coating to improve photolithographic precision during patterning of the metal interconnect component, as well as buffering the top of the metal interconnect component from harmful reactions with the Fluorine gas. In the case of an unlanded via, however, the sidewalls would remain exposed during the tungsten deposition in the via absent further measures.
There have been several conventional measures engaged in to protect the sidewalls of metal interconnect components from harmful reactions during the formation of via material. Many involve the formation of a barrier metal on the side walls using Chemical Vapor Deposition (CVD) process. CVD processes tend to be quite expensive to implement since CVD apparatus are quite expensive and occupy significant and precious real estate in a fabrication plant.
Other conventional techniques involve forming several barrier layers or different materials on the sidewalls. This works, but includes a number of fabrication steps thereby increasing the cost of fabrication and introducing new factors for yield reduction. Accordingly, what would be advantageous are methods for protecting the sidewall of a metal interconnect component for unlanded vias without requiring Chemical Vapor Deposition (CVD) processes or multiple barrier metals for protecting the sidewall.